The present invention relates to processes for designing mask layouts used in the fabrication of semiconductor devices. More particularly, the present invention relates to processes for designing mask layouts that are arranged in a hierarchical format.
Advances in photolithographic techniques have resulted in decreases in the size of the features on a chip. The lateral dimensions of features are generally defined by photolithographic techniques in which a detailed pattern is transferred to a photoresist by shining light through a mask or reticle. As feature size has decreased, the number of features on a chip has increased. This has resulted in mask designs that are much larger and more complicated than earlier designs.
In recent years, phase shifting masks have been developed to improve photolithographic processes. Phase shifting masks increase image contrast and resolution without reducing wave length or increasing numerical aperture. These masks also improve depth of focus and process latitude for a given feature size.
With phase shift photolithography, the interference of light rays is used to overcome the problems of diffraction and improve the resolution and depth of optical images projected onto a target. With this technology, the phase of the exposure light at the target is controlled such that adjacent bright areas are preferably formed 180 degrees out of phase with each other. Dark regions are thus produced between the bright areas by destructive interference even when diffraction would otherwise cause these areas to be lit. This technique improves total resolution at the target.
In general, a phase shifting mask is constructed with a repetitive pattern formed of three distinct layers of material. An opaque layer provides areas that allow no light transmission. A first transparent layer provides areas which allow close to 100% of the light to pass through. A transparent phase shifting layer provides areas which allow close to 100% of the light to pass through but phase shifted 180 degrees from the light passing through the first transparent layer. The first transparent layer and the phase shifting layer are positioned such that light rays diffracted through each area are cancelled out in a darkened area between them. This creates a pattern of dark and bright areas which can be used to clearly delineate features of a pattern defined by the opaque layer on the semiconductor wafer. Another method of constructing a phase shifting mask utilizes a semitransparent layer to cause the phase shift.
One process for fabricating phase shifting masks uses a voting technique to fabricate a defect-free printing mask. The process includes forming an opaque layer on a major surface of a transparent substrate, patterning the opaque layer to expose portions of the underlying transparent substrate, forming a phase shifting mask layer to expose the portions of the underlying transparent substrate, phase-etching partway into the exposed portions of the transparent substrate by an amount equivalent to a preselected phase shift angle, and voting the phase shifting mask layer to accomplish the phase-etching in a series of steps, each equal to the phase shift angle, until a full 180.degree. phase shift is accomplished.
Other processes of fabricating phase shifting masks include those in which a transparent film is formed over a portion of a mask to create a phase shifting layer as well as the etching of phase shifting channels into the mask substrate.
Another method that has been developed to produce masks for use in the fabrication of semiconductors containing small features is optical proximity effect correction ("OPC"). In this method, changes are made to the binary mask layout so that it will print more clearly. Because of the limited resolution of current photolithographic tools (i.e., steppers), patterns defined on the photomask are transferred into the resist on the wafer with some distortions referred to as optical proximity effects. The main consequences in term of line width control are: comer rounding, difference between isolated and semi-isolated or dense patterns, lack of CD linearity where small features print even smaller than their expected size compared to large features and line end shortening where the length of a line having a small line width becomes smaller than its expected size. Moreover, optical proximity effects are convoluted with subsequent processing step distortions like resist processing, including dry etch and wet etch proximity effects.
In order to achieve a sufficient line width control at the wafer level, the mask designs are corrected for proximity effects, namely re-entrant and outside serifs are used to correct rounding and the edges of patterns are moved to correct line width errors.
Because of their complexity, mask designs are usually generated on a computer and stored in a large data file. As the number of features on a chip has increased, the size of these data files has increased. This has produced files that are so large that they have become cumbersome to work with. One process that has been used to reduce the size of the data file and improve its manageability is to divide the layout into a number of smaller units or cells which can be arranged in a hierarchical format. However, when it is necessary to make changes in the layout, the hierarchical structure must be expanded into planar form for the changes to be made and incorporated into the design. This has proven to be an unwieldy and time consuming process.
Accordingly, it would be significant advancement in the art to provide a process for correcting a hierarchical mask layout in which changes could be made efficiently at sublevels in the hierarchical structure without flattening the entire layout. Such a process is disclosed and claimed herein.